TLDR:

The deeper you look at accelerated computing, the more a simple truth emerges -- silicon alone is not the moat. The real lock on the market is how those chips talk to each other.

NVLink, NVIDIA's proprietary high-bandwidth interconnect, is the glue that turns otherwise discrete GPUs into one giant, coherent accelerator.

In the process, NVIDIA gains control over the most lucrative workloads in Artificial Intelligence (AI), High-performance computing (HPC), and visualization.

I try to distill a complex topic to the best that I can. We start by exploring the bandwidth bottlenecks that plague PCIe-based systems and how NVLink's point-to-point links and non-blocking NV Switch fabric rewrite the rules for multi-GPU scaling.¹

From there we dive into NVLink Chip-to-Chip (C2C), the Grace Hopper coherence layer that lets GPUs sip from CPU memory while burning roughly 25× less energy per bit than a PCIe hop.²

Alongside the architectural tour, we track the real-world consequences -- faster LLM training runs, shared VRAM pools for cinematic renders, and scientific simulations that no longer crawl.³

Table of Contents

Key Glossary: Interconnects and Related Jargon

We compare NVLink with other chip interconnects, like PCIe Gen5, CXL, and AMD's Infinity Fabric. The focus: which moves data fastest, which is lowest in latency, and which solutions tie you to a single vendor versus keeping your options open?

Then we follow how NVLink has changed from version 1.0 to 5.0, and how NVIDIA is now letting others use its new NVLink Fusion technology -- hoping to make it the standard way chips connect in mixed systems.

If you buy the argument that interconnect speed defines what problems you can solve, NVLink stops being a specs table entry. It becomes the real monopoly.

Chapter 1: What Is NVLink?

NVLink is NVIDIA's proprietary, high-speed, point-to-point interconnect designed to link GPUs (and increasingly CPUs) into a unified complex that behaves as a single accelerator.

Instead of routing traffic through the CPU's PCI Express (PCIe) root complex, NVLink creates direct peer-to-peer paths between devices. Each "link" is a bundle of high-speed differential lanes that aggregate into a mezzanine-style bridge between neighboring GPUs.

By the time you reach Blackwell-generation silicon, an NVLink endpoint can sustain up to 900 GB/s of bidirectional bandwidth per GPU without touching the PCIe fabric.

From Pascal through Blackwell, NVLink has followed a deliberate doubling cadence that keeps PCIe -- and anything built on top of it -- permanently behind. The table below recaps the progression alongside the PCIe era each generation leapfrogged.

The jump to 1.8 TB/s keeps a ≈14× headroom over PCIe Gen5 x16 (~128 GB/s), which is why trillion-parameter LLM training still requires NVLink-class collectives rather than commodity buses.

Switchless mesh, switch fabric, and scale

NVLink started out connecting GPUs together in simple mesh or ring layouts -- each GPU had direct connections to a few others, so they could send data straight across without waiting their turn on the PCIe bus.

Later, NVIDIA added a hardware switch (NV Switch) that let lots of GPUs talk to each other at once, instead of just in small groups. For example, one NV Switch can link up to 16 GPUs in a box, and all of them can share data at full NVLink speed without getting in each other's way.

This architectural choice solves three headaches endemic to PCIe-based clusters:

• Bandwidth: PCIe 5.0 x16 gives about 128 GB/s both ways; NVLink gives much more, so GPUs don't have to wait for data.⁴
• Latency: NVLink skips the CPU and is much faster inside the server -- delays drop to just a few microseconds.
• Coherence: NVLink keeps memory in sync between GPUs, so code can access GPU or CPU memory directly instead of copying data around.⁵

Beyond GPU-to-GPU: NVLink C2C

NVLink C2C (Chip-to-Chip) lets a Grace CPU and Hopper GPU connect directly, sharing memory at much higher speed and lower energy use than PCIe.

This means a GPU can use the CPU's memory when it runs out of local VRAM, without a big slowdown. So, bigger models can run without running into memory or power problems.

Why it matters

With NVLink, all the GPUs and CPUs act like one big team instead of isolated parts. This means the software can use all the hardware together, sharing memory and data fast. Important operations for AI training, like all-reduce and broadcasting, run quickly and smoothly. This leads to faster training, less wasted power, and easier programming.

NVIDIA's real advantage isn't just their software -- it's the speed, low lag, and efficiency of NVLink, which others haven't matched yet.

Chapter 2: Performance, Latency, and Power Efficiency

The economic penalty for skipping NVLink shows up long before a purchase order clears. Data center operators who wire their clusters with commodity PCIe interconnects discover two brutal truths:

• scaling stalls well below linear
• every idle microsecond bleeds watts.

2.1 The Energy Penalty

NVLink is built for fast, efficient data transfer; PCIe uses more energy per bit to move the same data.⁶ When transfers are slow, GPUs sit idle but still use power, so you pay extra both for the inefficient transfer and for hardware doing nothing. On big clusters, energy waste per useful compute skyrockets.

2.2 The TCO Calculation -- The Monopoly in Practice

At first, picking PCIe instead of NVLink seems like a smart cost-saving move. PCIe hardware is much cheaper up front, and the specs sound fast enough. But as soon as you start training a big model, the real costs show up.

Here's what happens:

• Slower Training: PCIe can't move data fast enough between GPUs, so jobs take way longer to finish. This means you wait extra days -- or even weeks -- to reach your goals, and miss out on new revenue or research because everything slips.
• Wasted Hardware: While GPUs are waiting to send or receive data, they burn power but don't actually compute. So you pay top dollar for GPUs that sit idle for a big chunk of time.
• Huge Power Bills: Longer training + idling GPUs = much higher electricity bills. The more you try to save on hardware, the more money you lose on operations.

Add it all up, and the “discount” vanishes fast. Over just a few projects, paying less up front can actually cost you more than the pricey NVLink setup. It's a hidden “tax”: wasted time, wasted energy, wasted hardware.

Here's the twist -- everyone says NVIDIA has a monopoly because of CUDA, but that's not really the trap. The real moat is NVLink. Their fabric unlocks performance you just can't get with PCIe, so you end up paying NVIDIA's prices whether you like it or not.

That's what makes this monopoly so deceptive: it hides in your power bills and your lost time, not just in hardware invoices.

Chapter 3: The Future of the Monopoly -- NVLink Fusion vs. CXL

Having won the present on raw performance, Nvidia can harden its moat by licensing the fabric selectively and turning NVLink racks into the default blueprint for hyperscale AI factories.⁷

3.1 NVLink Fusion

NVLink Fusion is NVIDIA's new initiative that lets selected partners connect their own custom chips -- like CPUs, AI accelerators, or other devices -- directly into NVIDIA's ultra-high-speed GPU fabric using special NVLink chiplets and interface blocks.

Think of NVLink Fusion as an adapter that allow third-party silicon to join NVIDIA's super-fast hardware club, but on NVIDIA's terms.

Normally, different chips in a server talk to each other using standard connections like PCIe, which is much slower and struggles to keep up with AI workloads.

NVLink Fusion gives partners access to pieces of the NVLink technology -- such as chiplets (tiny, modular hardware blocks), SerDes (high-speed data links), and the rack-wide switch that ties everything together.

But crucially, NVIDIA does not hand over the full control of the underlying protocol, keeping the essential DNA of NVLink proprietary.⁸

3.2 The Challenger: CXL

CXL (Compute Express Link) is an industry-standard, high-speed interconnect protocol designed for coherently linking CPUs, GPUs, FPGAs, accelerators, and memory devices within servers and data centers.

It rides atop the PCIe physical layer (currently Gen5 and Gen6), but adds advanced memory coherency, direct load/store access, and fine-grained resource sharing between heterogeneous devices.

Unlike PCIe, which is optimized for general I/O and discrete transfers, CXL excels at pooling memory and connecting devices in a more unified, flexible memory space—allowing system RAM, persistent memory, and accelerator memory to be shared or accessed transparently by multiple components.

This lets disaggregated servers and accelerators dynamically compose resources for workloads, particularly in cloud and inference environments, with much more flexibility than legacy architectures.

4.3 The Enduring Monopoly

NVLink's future is a two-track play:

• invite partners into the rack while keeping the only highway that makes the rack economic.¹²
• Fusion taps custom silicon, CXL absorbs the commodity edge
• NVIDIA keeps the 14× bandwidth differential that dictates performance-per-watt in training clusters.

Conclusion

If you strip away the marketing wars and the surface-level focus on flops, CUDA, or even raw chip supply, the reason NVIDIA dominates AI isn’t just better silicon or clever software lock-in -- Its NVLink

The connective tissue that lets every dollar spent on compute deliver maximum throughput, minimal waiting, and scale that simply isn't feasible with PCIe or open standards alone.

At the start, I argued that interconnect speed defines what problems a datacenter can solve.

After examining the arc from PCIe bottlenecks to NVLink’s peer-to-peer fabric, and from NVSwitch and C2C to Fusion, the pattern is clear.

As other vendors talk about “openness,” NVIDIA has built a network that bakes their advantage right into the server rack. It’s not just about making their own GPUs faster; it’s about making any alternative uneconomical at serious scale.

While headlines cite CUDA as the moat, NVLink is the underwater reef that breaks any vessel not designed for NVIDIA’s ocean.

No competitor -- not CXL, not PCIe, not open accelerators -- can yet offer the seamless, ultra-low-latency, and high-bandwidth connections required for the largest AI models (and the biggest AI customers).

By licensing Fusion and letting others “plug in,” NVIDIA appears open, but the only highway that makes hyperscale AI profitable is still theirs.

As AI gets hungrier for bandwidth and systems grow ever larger, every new rack, every new standard, reinforces this advantage.

Even if you swap out the CPU or buy next year’s “open” accelerator, your data will still flow through NVLink’s lanes, routed by NVIDIA’s own switch fabric.

The AI race isn’t just about who makes the fastest chip -- its now about who owns the roads connecting them.